In television receivers, and the like, it is common practice to employ a digital phase-lock-loop (PLL) frequency synthesiser as part of the front-end tuning circuit. It is a problem, in these receivers, that tuning can be relatively coarse, especially where the implementation is of a low-cost simple construction.
Also due to component drift with ageing the comparison reference frequency may drift or become noisy so causing errors in the synthesised local oscillator frequency.
A further problem arises with these systems when they are used to demodulate r.f. signals from a low quality source, where the actual frequency may be time dependant.
A known improvement upon the aforesaid incorporates a combination of digital and analogue control circuits, employed in tandem. In this arrangement the local oscillator frequency is controlled by a digital P.L.L. until it comes within capture range of the analogue circuit. Subsequently, the variable frequency oscillator is controlled by the latter circuit. A lock detect circuit has been used thus to monitor the performance of the digital PLL and to transfer control to the analogue circuit once `in-lock` has been attained.
Hitherto, such lock-detect circuits have not been without shortcomings. In particular, such lock detect circuits used in phase comparators can be inherently poor indicators of lock being achieved since in general they:
(i) do not accurately define the lock window;
(ii) in variable reference frequency (f ref) systems the actual lock varies with f ref;
(iii) they are prone to producing spurious `in-lock` signals when the system is in fact out of lock unless external circuitry (hence extra device pins) is used to correct this fault;
(iv) Analogue lock detect circuits are inherently complex in their operation and also require external components, and,
(v) in some digital systems the lock window is highly process dependant.